FEROL (and its bothers MOL)

In 2014, the Myrinet seats on the FRL card was replaced by the FEROL (FrontEnd Readout Optical Link).


The first prototype (named MOL : Multi Optical Link) based on PCIe bus (8 lanes) was used to design protocols and to test the implementation of high speed optical link (4 links @ 8 Gb/s and 1 @ 10 Gb/s).

The test done so far are:

The 5 Gb/s link protocol that will be used between FED (SLINKXpress) and the DAQ. (see talk (1)).

As presented in the talk above, the protocol used is home-made and done to be able to retransmit data in case of an error on transmission. The link is also used to request status and send command from DAQ side to FED card (to control and monitor the protocol engine.

A fedkit was developed to help FED people to integrate their hardware. Here are some details about that:


The 10Gb/s link will use the standard TCP/IP imlpemented in VHDL in the FPGA, no processor to manage the link. (see Petr presentation (2)).

Some eye measures were done on the MOL (thank's to Jan Troska and  Csaba Soos) :


5Gb electrical eye10 Gb electrical eye

All document related to the PCB can be found on EDMS

 Documentation (Address table)

FEROL firmware version

Data base for test_benches results